1. Field of the Invention
The present invention relates to direct digital frequency synthesis, and more particularly, to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency, which is capable of synthesizing analog signals with high quality without performing complicated gradient calculation requiring a separate base decoding, and a synthesizing method thereof.
2. Description of the Related Art
With the necessity of high speed processing systems with advances in information & communication technologies, there is an increasing need for high speed digital frequency synthesis systems which are capable of synthesizing a desired frequency at a high speed.
In general, a frequency synthesis system includes a direct frequency type and an indirect frequency type. The indirect frequency type, such as a phase locked loop (PLL) frequency synthesizer, requires a voltage controlled oscillator (VCO), thereby producing phase noises, and has a feedback loop, thereby providing great latency for frequency synthesis as well as providing coarse frequency resolution. For the purpose of overcoming this problem, there have been mainly used direct digital frequency synthesizers with small latency for frequency synthesis, low phase noise, and relatively fine frequency resolution for precise and high speed frequency synthesis.
Since a direct digital frequency synthesizer (DDFS) is capable of instantaneous phase and frequency conversion over a wide band and provision of correct phase and frequency without signal discontinuity owing to a merit of digital, it is suitable for high speed precise frequency synthesis and is mainly applied to radars and wireless communications requiring high speed phase and frequency hopping. The direct digital frequency synthesizer has an increasing application range to various fields for applications by simplifying its hardware configuration and hence reducing production costs. In addition, since portions, except for a digital to analog converter (DAC), are implemented by digital circuits, use of DDFSs is on the rise with increase of integration of semiconductor integrated circuits.
FIG. 1 shows a general DDFS configuration. As shown, a DDFS includes a phase accumulator 10 for accumulating frequency control words (FCWs) to generate new phase data for each sampling clocks with phase angles (0 to 2π) around a circle through overflow, a phase to amplitude mapper (PAM) for discretely mapping the phase data provided by the phase accumulator 10 onto amplitudes corresponding to sine waves, and a digital to analog converter (DAC) 30 for converting discrete amplitudes provided by the PAM 20 into an analog signal having a desired frequency form.
Methods of mapping phase onto amplitude in the PAM 20 may include, for example, a method of using a read only memory (ROM), a method of using Taylor series, a method of using a coordinated rotation digital computer (CORDIC), etc.
Although the method of using ROM provides various schemes for size reduction, this method is still low in space efficiency and has additional complicated circuits for size reduction, thereby consuming much power. Therefore, the method of using Taylor series or the method of using CORDIC has been indeed used to minimize the use of ROM.
However, both of the method of using Taylor series and the method of using CORDIC require a very complicated operation configuration and still a ROM of a look-up table scale, thereby still raising a problem of high power consumption and delay due to complexity without providing particular integration efficiency.
FIG. 2 shows a configuration of DDFS using a sine-weighted DAC for directly converting an output of a phase accumulator into a sine waveform without using the above-mentioned PAM. As shown, the above-described complicated configuration can be simplified by applying a sine-weighted DAC 50 for outputting sine waves in a manner to selectively switch current sources configured to be adapted for sine waves using phase information provided by a phase accumulator 40.
However, in this case, the configuration of current sources for generating precise sine waveforms is difficult to be achieved with increase of a resolution and requires an exponential increase in area. For example, a configuration of DDFS having a resolution of 9 bits or so requires hundreds of switches and current sources having different weights, which results in difficulty in its design and increase in its required area.
In recent years, in order to alleviate the above-described problems, there has been employed a scheme of configuring a PAM for converting FCW into binary codes having an amplitude of a sine waveform and configuring a linear DAC for converting the binary codes into a sine wave using a control unit having relatively low complexity.
FIG. 3 shows an example configuration of a conventional direct digital frequency synthesizer in which phases provided by a phase accumulator are mapped onto binary codes and a linear DAC for generating an output based on the binary codes is applied. As shown, the conventional direct digital frequency synthesizer includes a PAM 160 for generating binary codes using phase information provided by a phase accumulator 110, and a linear DAC 170 for converting the binary codes output from the PAM 160 into an analog signal. The PAM 160 includes a base decoder 130 for generating base point information to set a basic position of amplitude using some upper bits of output bits of the phase accumulator 110, a gradient generator 150 for generating a gradient to set an extension amplitude value for linear approximation in conformity to a sine waveform between base points using lower bits of the output bits of the phase accumulator 110, and complementors 120 and 140 for extensionally map ¼ sine wave amplitude information obtained by the base decoder 130 and the gradient generator 150 onto a sine wave of one period as a whole using two most significant bits of the phase accumulator 110.
The above-described method is a method of setting positions of base amplitudes by means of the base decoder 120 and approximating a gradient interconnecting points between the set base amplitudes (that is, coarse segments for amplitude) by combining a plurality of gradient values, thereby generating final binary information in the PAM 160 in consideration of all of them.
Although the above-described method may configure a DDFS with no ROM, it requires pipelines of a considerable size for high speed operation and still has a problem of configuration of complicated operators.
That is, a considerably complicated logic configuration is required for the base decoder 42 for obtaining base points, and large-scaled pipelines are required for its output. In addition, an operator having the same size as output bits of the base decoder 120 is required for operation of such base points and gradients, and also pipelines are required accordingly, which results in complexity of configuration. Such complexity of configuration leads to low integration, high costs, high power consumption and operation delay. Accordingly, such an existing complicated configuration has to be simplified for expansion of an application range of DDFS.
In the end, there is a need of DDFS of a new form which is capable of increasing integration, saving power and maintaining or improving output quality by overcoming such configuration complexity and simplifying a configuration of PAM, which occupies the most portion of an actual total area, to decrease its area.